The present invention relates to a semiconductor design technology, and more particularly, to a technology for forming an electrostatic discharge protection circuit of a semiconductor device.
A gate oxide layer of a metal oxide semiconductor (MOS) element, among the internal circuits of a semiconductor device, has a problem of easily being destroyed by electrostatic discharge (ESD), because of high input impedance of a gate. Since the thickness of the gate oxide layer of a transistor in an internal circuit is reduced to manufacture a high performance and highly integrated semiconductor device, it is necessary to dispose an electrostatic discharge protection circuit in a semiconductor device for protecting an internal circuit thereof from the electrostatic discharge.
An electrostatic discharge standard model is used for evaluating durability and performance of an electrostatic discharge protection circuit and for analyzing the effect of electrostatic discharge on an internal circuit. In general, three electrostatic discharge standard models have been introduced. They are described hereinafter.
The first general electrostatic discharge standard model is a human body model (HBM). The HBM is a model for simulating the discharge that might occur when a human touches a semiconductor device. The second general electrostatic discharge standard model is a machine model (MM). The MM is a model for simulating the discharge when a metallic machine touches a semiconductor device in a semiconductor device manufacturing process. The third general electrostatic discharge standard model is a charged device model (CDM). The CDM is a model for discharging electrostatic charge in a semiconductor device to an external ground or an external conductor in a semiconductor memory fabricating process such as a package assembly process.
The electrostatic discharge protection circuit is manufactured with a grounded gate MOSFET (ggMOS), a gate-coupled MOSFET (gcMOS), a bipolar junction transistor (BJT), a diode, or other metal-oxide-semiconductor elements, which makes excess current flow to a power source by clamping a constant voltage using a parasitic bipolar junction transistor (BJT) that is internally generated when electrostatic discharge is generated. Since the electrostatic discharge protection circuit may make supplementary influence such as leakage current as a kind of parasitic capacitance component when the electrostatic discharge dose not occur, the size and the number of the electrostatic discharge protection circuits should be properly controlled.
Since the semiconductor device determines the logical level of an input signal, for example, an ADDRESS signal, a COMMAND signal, or a DATA signal, based on a reference voltage, the semiconductor device includes a plurality of input buffers for detecting each of the input signals. An input buffer for detecting a logical level of an input signal based on a reference voltage is defined as a pseudo differential type buffer and is internally formed as a differential amplification circuit that receives an input signal and a reference voltage.
FIG. 1 is a diagram illustrating a semiconductor device according to the related art.
Referring to FIG. 1, the semiconductor device includes: a plurality of pads for receiving a reference voltage VREF and a plurality of input signals IN1 to INi; a plurality of input buffers 121A to 121I for receiving the reference voltage VREF and a corresponding input signal; a plurality of external electrostatic discharge protectors 101A to 101I, and an external electrostatic discharge protector 102 connected to the transmission path of a reference voltage VREF and a corresponding input signal for protecting the plurality of input buffers 121A to 121I from the external electrostatic discharge; and a plurality of internal electrostatic discharge protectors 111A to 111I and 112A to 112I connected to the transmission path of the reference voltage VREF and a corresponding input signal for protecting the plurality of input buffers 121 to 121I from internal electrostatic discharge.
The external electrostatic discharge protectors 101A to 101I and 102 are disposed adjacent to the pad because they are electrostatic discharge protection circuits corresponding to the HBM and the MM. The internal electrostatic discharge protectors 111A to 111I and 112A to 111I are disposed adjacent to an input buffer because they are electrostatic discharge protection circuits corresponding to the CDM. Therefore, one external electrostatic discharge protector and a plurality of internal electrostatic discharge protectors as many as the number of input buffers are disposed at (connected to) the transmission path of the reference voltage VREF while one external electrostatic discharge protector and one internal electrostatic discharge protector are disposed at (connected to) the transmission path of each input signal.
Therefore, greater parasitic capacitance component may be generated and the current may be badly leaked at the transmission path of the reference voltage compared with the transmission path of the input signal. If even one of the internal electrostatic discharge protectors is defected, the reference voltage VREF may be internally distorted.
The input buffer of the semiconductor device according to the related art will be described hereinafter.
FIG. 2 is a circuit diagram illustrating the input buffer of FIG. 1.
Referring to FIG. 2, the input buffer includes a current mirroring unit 210 connected between a power source voltage end VDD and both a first connection end N1 and an output end N0, a first input transistor MN1 connected between the first connection end N1 and a second connection end N2 and controlled based on a reference voltage VREF, a second input transistor MN2 connected between the output end N0 and the second connection end N2 and connected by an input signal INi, and a bias transistor MN3 connected between the second connection end N2 and a ground voltage end VSS controlled by an enable signal EN.
The input buffer further includes an inverter INV1 for inverting a signal outputted from the output end N0, a first transistor MP1 connected between the power source voltage end VDD and the first connection end N1 and controlled by the enable signal EN, and a second transistor MP4 connected between the power source voltage end VDD and the output end N0 and controlled by the enable signal EN.
In the input buffer, the first input transistor MN1 is an NMOS transistor that receives the reference voltage VREF as the input of the gate, and the second transistor MN2 is an NMOS transistor that receives the input signal INi as the input of the gate. Therefore, the first and second input transistors MN1 and MN2 may be electrostatic discharge sensitive elements, and the external and internal electrostatic discharge protectors protect the first and second input transistors MN1 and MN2.
As described above, the semiconductor device according to the related art includes a plurality of input buffers for detecting each of input signals INi based on the reference voltage VREF and a plurality of internal electrostatic discharge protectors at the transmission path of the reference voltage VREF for protecting electrostatic sensitive elements from the electrostatic discharge. Therefore, the size of the semiconductor device according to the related art increases. The semiconductor device according to the related art has greater parasitic capacitance and bad current leakage compared to other input signals. Therefore, the semiconductor device according to the related art may include defects.